In the semiconductor integrated circuit (IC) industry, technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of IC processing and manufacturing.
One type of transistor that helps enable such scaling down is a stacked nanowire transistor. In a stacked nanowire transistor, the channel is made of one or more elongated semiconductor features, each of which is entirely or partially surrounded by the gate structure. Such elongated semiconductor features may also be referred to as nanowires. The nanowires for a single transistor may be vertically stacked.
Various transistors within an integrated circuit serve different functions. For example, some transistors are designed for input/output operations. Some transistors are designed for core processing operations. Some transistors are designed for memory storage operations. While it is desirable that such different transistors have different functions to better serve their purposes, it can be difficult to manufacture multiple stacked nanowire transistors in a single circuit.